pocSRAM

The pocSRAM is a Proof of Concept of our SNESRam idea.

The microcontroller fills RAM with the gamerom-data, then isolates it's bus and maps the SRAM into the SNES adressspace. The pocSRAM is designed to use only a few IO-pins on the uC-side to adress 4MB of SRAM. We use 8* 512kbyte RAM-chips, that means 19 adresslines ,8 chipselects and 8 data. Due that we only need incremental RAM-access for loading ROM-images to RAM, (perhaps with some offsets for patches later on) its easier to put a preloadable 24bit counter to A0-A18 and increment the adress every write cycle. The counter is preloaded via a 24bit serial shift-register, that means only 5 pins to access 19bit of adresses:

3 for the shift register:

• DATA
• CLK
• LATCH

2 for the counter:

• UP
• PRELOAD

The databus is connected directly to the uC, which means 8 additional I/O pins.

8 for the datalines:

• D0-D7

CS is multiplexed and can either be connected to the counter or to 3 additional I/O pins. The address- but also the databus is driven by tristate bus-drivers, which turn to tristate when the microcontroller hands the RAM over to the SNES. This is to avoid conflicts on the lines.