MINimal IR

MinIR is intended to provide a minimalist textual machine level intermediate representation to be used as an interchange format between compiler back-ends and experimental tools.

Download Sources

Anonymous mercurial access: http://hg.assembla.com/minir-dev
Browse the repository: http://trac-hg.assembla.com/minir-dev/browser

Continuous Integration Server

The main branch is monitored by a continuous integration server:
https://compilation.ens-lyon.fr/hudson/job/minir-master/

Publications

• MinIR: a Minimalistic Intermediate Representation [paper] [slides]
  Julien Le Guen, Christophe Guillon, Fabrice Rastello
  Workshop on Intermediate Representations (WIR'11)
  Chamonix, France, 2011

• Tirex: A Textual Target-Level Intermediate Representation for Compiler Exchange [paper] [slides]
  Artur Pietrek Florent Bouchez Benoît Dupont de Dinechin
  Workshop on Intermediate Representations (WIR'11)
  Chamonix, France, 2011
  Note: Tirex can also mean "Tirex is a minIR EXtension," it is based on MinIR and adds to it the program data and loop information.

The current experimental tool is a prototype for register coalescing with aliasing constraints in the context of decoupled register allocation approach: First the register pressure is lowered (using puzzle solver to measure the register pressure), then the program is dump in MinIR. nOptionally the assignment given by the compiler back-end is also dump.

MinIR is based on Yaml serialization format: http://en.wikipedia.org/wiki/YAML. A hash table is represented as {key1: value1, key2: value2, ...}. An array is represented as [ value1, value2, ... ]. The elements of arrays/hashs can also be listed in a one element per line way using "-" for arrays.

In this format:

• a register class (see examples/arm-registers.min) can be either a list of registers (eg registers: [S0, S1, S2,...]) or a union of some other register classes (eg classes: [ R, S, D, Q ]). The aliasing is represented using a mapping (eg D0: [S0, S1] says that D0 contains S0 and S1).
• a function (see examples/arm-diagonal-interpolation.min) has a list of basic blocks. Each basic block having a label used in jump (eg{ op: bgt, fallthru: exit, target: line_loop, uses: [ FR ] }) or in phi functions (eg { defs: [in2.R], op: phi, uses: [ in1.R<interpolate>, in3.R<line_loop> ] })
• for each variable the register class in which it can be allocated is provided in the hash table vars (eg. vars: { out: p32, outw: i32, in: p32 ... })
• an instruction has a list of definited variables (defs), a list of used variables.
• an operand v.Q means that variable v have to be on register class Q on this operand. Q can be a register (eg out.R0)
• an instruction has also a list of implicit definitions (implicit_defs) that appear semanticaly before the definition point in the instruction. This is useful for example to represent scratch registers eg(see http://trac-hg.assembla.com/minir-dev/browser/tests/test3.min ) as follow implicit_defs: [v3.R1<dead>].

There are still a few Todos.